1. Field of the Invention
The present invention relates to memory array organization, and particularly to those memory arrays organized as a plurality of pages.
2. Description of the Related Art
Integrated circuit memory arrays are encountered in both specialized memory devices and in other more general integrated circuits. An address presented to the memory device (or memory sub-system within a more general integrated circuit) is usually decoded to select one or more memory cells corresponding to each given address. For example, many memory devices have byte-wide data paths, and each unique address usually selects eight different memory cells, which may be located adjacent to each other in one array, physically distributed within one array, or physically distributed in up to eight different sub-arrays. Some devices store more than one bit of information into a single memory cell, and thus obviously require less than eight memory cells to store a byte of information.
Irrespective of the internal architecture of a memory array (i.e., whether implemented as a single array or as many sub-arrays, whether an addressable byte is stored in contiguous memory cells within one array or distributed throughout more than one sub-array), many memory arrays may be conceptualized as being organized as a plurality of rows and a plurality of columns with one or more memory bits stored at each addressable row and column intersection.
Many memories may also be conceptualized as having a plurality of pages, each containing a plurality of locations within the page An address for such a memory specifies a page (which may also be viewed as a ‘row’ address) and an offset or location within the page (which may also be viewed as a ‘column’ address). Most memories are organized with a number of rows equal to an integral power of two, such as 217 (i.e., 131,072 pages) and a number of columns also equal to an integral power of two, such as 29 bytes (i.e., 512 bytes). An integral power of two may also be termed an ‘even binary number.’ Examples includes 16 (i.e., 24) and 128 (i.e., 27) but not 24 (i.e., 24+23).
For example, some commercial ‘Flash’ EPROM devices, such as the 64 MB Toshiba TH58512FT, are organized as a plurality of 528-byte pages, which are accessed byte-serially by page. Of this page, 512 bytes are normally used for general storage, while the additional 16 bytes are provided for other specialized use, such as redundancy. Such a page size may be thought of as a basic page of 512 bytes, and an extended page adding another 16 bytes, for a total of 528 bytes per page. This extended page space adds about 3% more memory cells to the array. Unfortunately, many users do not utilize such an extended page space, frequently because the resulting page size of 528 bytes is not a power of two (and thus not a traditional binary ‘boundary’) consequently wasting the additional 3% area required to implement the extended page memory cells. Yet for compatibility reasons, many devices still implement such additional memory cells.
In addition, many Flash devices reserve a portion of its pages for use in replacing pages that, when tested or later programmed, are discovered to be defective. For example, in many 64 MB devices, up to 2-3% of all memory pages are reserved for redundancy, and the total amount of memory guaranteed to be fully functional after programing accordingly reduced. In a memory device with fewer defective pages than the reserved number set aside for such purposes, the remaining reserved pages may easily be wasted as well because they are not guaranteed to be available. Consequently, upwards of another 2-3% of memory cells physically implemented in the memory device may be wasted.